1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device, and in particular, to a method of forming an STI (Shallow Trench Isolation) structure, to a method of forming a PMD (Pre-metal Dielectrics) film, and to a method of forming a passivation film.
2. Description of the Related Art
The STI structure is extensively employed for the isolation of elements in recent semiconductor devices. This STI structure can be formed by a method wherein a trench is formed in an element isolation region of a semiconductor substrate, and then, for example, a silicon oxide (SiO2) film functioning as an element isolating insulation film is buried inside this trench. Concomitant with advancement in fineness of semiconductor elements in semiconductor devices, the aspect ratio of the trench inevitably becomes larger, so that it is now becoming increasingly difficult to bury the conventional ozone (O3)-TEOS CVD-SiO2 film or HDP-TEOS CVD-SiO2 film in the trench of STI structure without inviting the generation of voids or seam.
Therefore, in the manufacture of a semiconductor device where the fineness of semiconductor elements is in the order of 100 nm or less, there has been proposed a method wherein a coating type solution is employed for burying an element isolating insulating film in the STI trench.
This method will be explained with reference to FIGS. 1A to 1F. First of all, as shown in FIG. 1, an SiO2 film 101 is deposited on the surface of a silicon substrate 100, and then an Si3N4 film 102 functioning as a mask member is laminated on the SiO2 film 101. Subsequently, by using the ordinary exposure technique and dry etching technique by RIE (Reactive Ion Etching) method, the Si3N4 film 102, the SiO2 film 101 and the silicon substrate 100 are successively worked to form an STI trench 103 for forming STI element isolation in the silicon substrate 100. In this case, the size of the STI trench 103 is: about 100 nm in width and about 300 nm in depth for instance.
Next, as shown in FIG. 1B, in order to enable the STI trench 103 to be completely buried, a solution of silazane perhydride polymer ((SiH2NH)n) is coated all over the surface of the Si3N4 film 102 to a thickness of about 600 nm by spin coating method for instance. Then, this coated film is subjected to baking treatment for about 3 minutes at a temperature of not higher than 200° C., for example about 150° C., to allow the solvent to evaporate, thus forming polysilazane (hereinafter referred to as PSZ) film 105.
This PSZ film 105 is then subjected to heat treatment for 60 minutes in an atmosphere containing water vapor at a temperature ranging from about 350° C. to 600° C. to convert this PSZ film 105 into an SiO2 film 106 as shown in FIG. 1C.
Thereafter, as shown in FIG. 1D, the SiO2 film 106 is subjected to heat treatment for about 30 minutes in an oxidizing atmosphere or in an inert atmosphere such as nitrogen gas atmosphere at a temperature of 900° C. or so. As a result, NH3 and H2O both left remained in the SiO2 film 106 are released therefrom, thus obtaining a high-density SiO2 film 107 which is higher in density than the SiO2 film 106.
Then, the SiO2 film 107 formed on the Si3N4 film 102 is selectively removed by CMP (Chemical Mechanical Polishing) method for instance to permit the surface of the Si3N4 film 102 to expose as shown in FIG. 1E. As a result, the SiO2 film 107 is formed inside each of the STI trenches 103 with only the surface of the SiO2 film 107 being exposed.
Further, the Si3N4 film 102 and the SiO2 film 101 are successively removed so as to permit the surface of the silicon substrate 100 to expose as shown in FIG. 1F. As a result, the STI structure where the SiO2 film 107 is buried inside the STI trench 103 is formed.
According to the aforementioned method, the PSZ film 105 existing inside the STI trench having a trench width of 1 μm or more can be sufficiently converted into the SiO2 film 107 in subsequent steps. In the case of the STI trench 103 where the trench width thereof is as narrow as about 100 nm or less however, part of the PSZ film 105a existing inside the trench cannot be sufficiently converted into SiO2 as shown in FIG. 1E, thereby generating an insufficiently-converted PSZ region 105a. Since this insufficiently-converted PSZ region 105a can be wet-etched at a high etching rate, it is difficult to inhibit the generation of a divot 108 particularly at each corner portion of the STI structure. Moreover, it is also difficult to control the height of the insulating film of the STI structure and therefore it has been difficult to realize an STI structure having a desired configuration.
The reason for this can be ascribed to the fact that in the case of the PSZ film 105 formed inside the STI trench 103 where the trench width thereof is as narrow as about 100 nm or less, it is difficult, as shown in FIG. 1C, to supply the PSZ region 105a located close to the bottom of the trench with a sufficient quantity of H2O and oxygen (O2) for enabling the PSZ region 105a to convert into the SiO2 film 106.
Therefore, there have been persistent demands for the development of a manufacturing method which makes it possible to uniformly convert the PSZ film existing inside the STI trench into an SiO2 film irrespective of the size of the STI trench width, i.e. not only an STI trench having a relatively wide trench width but also an STI trench having a narrow trench width of the order of 100 nm.
In the meantime, as for the materials for a PMD film, although P-TEOS SiO2 has been conventionally employed, the PMD film is required to have the following characteristics. Namely, the PMD film is capable of flattening step portions formed on an underlying layer such as gate electrodes, and this flattening by the PMD film can be performed at a low temperature of 600° C. or less. Further, the wet etching rate of the PMD film is as close as possible to that of thermally oxidized film. Namely, the purpose of this is to prevent the generation of a step portion which may be caused to occur on the occasion of permitting the surface of Si substrate to expose in a step of forming a contact due to abnormal etching of the sidewall of the contact in a wet etching treatment.
As promising material for low temperature PMD, a coating type film such as SOG can be employed. A coated film of SOG can be formed by a coating method over a stepped surface of a gate electrode with an interlayer insulating film such as an SiO2 film or an Si3N4 film being interposed therebetween. Although it is possible with the employment of this coating type film to obtain a flat film over an underlying surface region where the step portions are densely formed, it is impossible to obtain a flat film over an underlying surface region where the step portions are dispersedly formed. Furthermore, the conventional SOG film is defective in that a considerable degree of volumetric shrinkage of film is caused to occur on the occasion of removing the solvent contained in the SOG, thereby raising a problem that the SOG film is caused to crack at a region thereof where the coating of SOG film is relatively large in thickness. Additionally, even if this SOG film is converted into an SiO2 film through the heat treatment thereof, the wet etching rate of the converted SiO2 film is not less than twice as large as that of the thermally oxidized film. As a result, there is a problem that a step portion is caused to generate on the sidewall of the contact on the occasion of wet etching.
With respect to the formation of a passivation film, it has been difficult to realize an SiO2 film which is excellent in coverage and is free from plasma damage. Next, a passivation film of a 2-ply structure consisting of a P-TEOS SiO2 film and a P—SiN film that has been conventionally employed will be explained with reference to FIGS. 2A to 2C. First of all, as shown in FIG. 2A, a plasma (P) SiO2 film 203 is deposited on the surface of an interlayer insulating film 201 provided with a wiring 202 by HDP for instance. Due to poor coverage, the P—SiO2 film 203 is deposited relatively thick over the wiring 202 and relatively thin over the region located between wirings. Moreover, since the P—SiO2 film 203 is relatively high in moisture permeability, a P—SiN film 204 which is low in moisture permeability is deposited on the surface of the P—SiO2 film 203 as shown in FIG. 2B. Since this P—SiN film 204 is also poor in coverage, this P—SiN film 204 is deposited relatively thick over the wiring 202 as shown in FIG. 2B. Since this P—SiN film 204 is required to be deposited to a thickness of at least 100 nm in order to ensure low moisture permeability, the film thickness of this P—SiN film 204 over the wiring 202 becomes relatively large. As a result, as shown in FIG. 2C, the film thickness of the region where via-hole 205 is to be formed becomes relatively large, thereby making it difficult to form the via-hole 205 without increasing the aspect ratio.
In the case of the conventional SOG (Spin on Glass) also, it is required to make the film thickness thereof relatively large in order to level out the step portions originating from the wiring layer 202. As a result, as shown in FIG. 3B, there is a problem that the aspect ratio of the via-hole 205 becomes relatively large.
As explained above, the conventional methods are accompanied with problems that a divot is caused to generate in the width of STI trench of not more than 100 nm or so, and that due to the fluctuation in burying height of insulating material depending on the width of the STI trench, it has been difficult to realize a desirable STI structure. Further, in the case of the PMD film, it is difficult to concurrently achieve not only the flattening of the surface thereof at low temperatures but also a wet etching rate thereof which is almost identical with that of the oxide film.
With respect to the formation of a passivation film also, no one has yet to realize an SiO2 film which is excellent in step coverage and is free from plasma damage.